1.counter.v module counter(clk,rst_n,en,led); input clk; input rst_n; input en; //使能信号 output [3:0]led; //4个led灯 reg [17:0]cnt; //计数器 reg [3:0]led_r; parameter cnt_max = 24'd2_499_999; //led每个50ms变化一次(20*2499_999 = 50_000_000ns) always @(posedge clk or negedge rst_n) if(!rst_n) cnt <= 23'd0; else if(en) begin if(cnt == cnt_max) cnt <= 23'd0; else cnt <= cnt + 1'b1; end else cnt <= 1'b0; always @(posedge clk or negedge rst_n) if(!rst_n) led_r <= 4'b1110; //led_r低电平点亮 else if(cnt == cnt_max) led_r <= {led_r[0],led_r[3:1]}; //循环右移点亮一位led灯 else led_r <= led_r; assign led = led_r; endmodule 2. counter_tb.v `timescale 1ns/1ns //`define clk_period 20 module counter_tb(); reg clk; reg rst_n; reg en; wire [3:0]led; //counter counter0(.clk(clk),.rst_n(rst_n),.en(en),.led(led)); initial clk = 1; //always #10 clk = ~clk; initial begin rst_n = 0; en = 0; #10 rst_n = 1; #10 en = 1; #2000 $stop; end always #10 clk = ~clk; counter u1(clk,rst_n,en,led); endmodule 3.波形图 在work下无counter_tb.v和无波形。
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